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14/12/10-bit, 1200 msps d/a converters preliminary technical data ad9736/ad9735/ad9734 features ? 1.8/3.3 v dual supply operation ? ad9736 sfdr > 53 dbc to f out = 600 mhz ? ad9736 imd > 65 dbc to f out = 600 mhz ? ad9736 dnl = 1.0 lsb ? ad9736 inl = 2.0 lsb ? low power: 380 mw (i outfs = 20 ma; f out = 330 mhz) ? lvds data interface with on-chip 100 ? terminations ? analog output: adjustable 10-30ma (rl=25 ? to 50 ? ) ? on-chip 1.2 v reference ? 160 pin bga package applications ? instrumentation ? automatic test equipment ? radar ? avionics ? wideband communications systems: point-to-point wireless lmds pa linearization product description the ad9736, ad9735, and ad9734 are high performance, high frequency dacs that provide sample rates of up to 1200 msps, permitting multi-carrier generation up to their nyquist frequency. the ad9736 is the 14 bit member of the family, while the ad9735 and the ad9734 are the 12 and 10 bit members, respectively. they include a serial peripheral interface (spi) port that provides for programming many internal parameters and also enables read-back of status registers. they use a reduced specification lvds interface to minimize data interface noise that may degrade performance. the output current can be programmed over a range of 10ma to 30ma. the ad9736 family is manufactured on a 0.18 m cmos process and operates from 1.8v and 3.3v supplies for a total power consumption of 380mw in bypass mode. it is supplied in a 160 pin bga package for reduced package parasitics. functional block diagram lvds receiver synchronization bandgap dataclk_in+ dataclk_in- db[13:0]- db[13:0]+ clock distribution spi 14,12,10-bit dac iouta ioutb 2x sdo sdi sclk csb lvds dr iver controller reference current clk- clk+ rset vref reset dataclk_out+ dataclk_out- s1 s2 s3 c1 c2 c3 c2 c1 s1 s3 s2 c3 figure 1. functional block diagram product highlights ultra-low noise and intermodulation distortion (imd) enable high quality synthesis of wideband signals at intermediate frequencies up to 600 mhz. double data rate (ddr) lvds data receivers support the maximum conversion rate of 1200 msps. direct pin programmability of basic functions or spi port access for complete control of all ad9736 family functions. manufactured on a cmos process, the ad9736 family uses a proprietary switching technique that enhances dynamic performance. the current output(s) of the ad9736 family can be easily configured for various single-ended or differential circuit topologies. rev. pr j 9 / 7/2004 information furnished by analog devices is believed to be a ccurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks an d registered trademarks are the property of their respective companies. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.326.8703 ? 2004 analog devices, inc. all rights reserved.
ad9736/ad9735/ad9734 preliminary technical data rev. prj | page 2 of 42 table of contents ad9736/ad9735/ad9734specifications ........................................3 dc specifications ......................................................................3 digital specifications............................................................4 ac specifications.......................................................................5 explanation of test levels ................................................5 pin function descriptions......................................................6 pin configuration........................................................................7 package outline.............................................................................9 ordering guide ...................................................................................9 typical performance characteris tics........................10 spi register map ............................................................................14 spi register descriptions........................................................15 general description ..............................................................................19 serial peripheral interface................................................................19 ad9736 data interface controllers ....................................................22 ad9736 lvds sample logic...........................................................23 ad9736 sync logic and controller .............................................25 ad9736 digital built-in self test........................................................27 ad9736 analog cont rol register .......................................................28 voltage reference...................................................................................29 applications information .....................................................................30 ad9736 evaluation board schematics ...............................................31 ad9736 evaluation board pcb layout..............................................36 revision history revision pra: initial version revision prb: updated data based on initial evaluation results revision prc: updated data for web display and ongoing evaluation results revision prd: added spi port information revision pre: cleaned up spi port tables, added ad9736 rev a evaluation board schematics revision prf: added bga package outline drawing revision prg: added package pinout revision prh: added spi port description revision pri: edits for readability and clarity, added idd typical values and plots, updated spi register tables, added lvds an d sync controller sections, added pin function table, added bist description, added analog control section, added vref section, updated eval board schematic and pcb layout revision prj: update bist information, update spi definition to include sclk edge change for read operation, add spi timing, a nnotate schematic to show component values for output circuit, update aclr plots, add pcb fabrication details.
preliminary technical data ad9736/ad9735/ad9734 rev. prj | page 3 of 42 ad9736/ad9735/ad9734specifications 1 dc specifications (vdda33 = vddd33 = 3.3 v, vdda18 = vddd18 = vddc lk = 1.8 v, maximum sa mple rate, fs = 20ma, 1x mode, 25 ohm 1% balanced load, unless otherwise noted) ad9736 ad9735 ad9734 parameter temp test level min typ max min typ max min typ max unit resolution 14 12 10 bits integral nonlinearity (inl) 2.0 tbd tbd lsb accuracy differential nonlinearity (dnl) 1.0 tbd tbd lsb offset error tbd tbd tbd % fsr gain error (with internal reference) 0.5 0.5 0.5 % fsr gain error (without internal reference) 0.5 0.5 0.5 % fsr full scale output current 10 20 30 10 20 30 10 20 30 ma output compliance range 1.0 1.0 1.0 v output resistance tbd tbd tbd k ? analog outputs output capacitance tb d tbd tbd pf offset tbd tbd tbd ppm/ c gain tbd tbd tbd ppm/ c temperature drift reference voltage tbd tbd tbd ppm/ c internal reference voltage 1.2 1.2 1.2 v reference output current 100 100 100 na vdda33 3.13 3.3 3.47 3.13 3.3 3.47 3.13 3.3 3.47 v analog supply voltages vdda18 1.70 1.8 1.90 1.70 1.8 1.90 1.70 1.8 1.90 v vddd33 3.13 3.3 3.47 3.13 3.3 3.47 3.13 3.3 3.47 v digital supply voltages vddd18 1.70 1.8 1.90 1.70 1.8 1.90 1.70 1.8 1.90 v bypass mode 380 380 380 mw fir interpolation filter enabled 550 550 550 mw power consumption standby power tbd tbd tbd mw idda33 25 tbd tbd ma idda18 47 tbd tbd ma iddd33 10 tbd tbd ma supply currents 1x mode iddd18 122 tbd tbd ma idda33 25 tbd tbd ma idda18 47 tbd tbd ma iddd33 10 tbd tbd ma supply currents 2x mode, interpoation enabled iddd18 234 tbd tbd ma table 1: dc specifications 1 specifications subject to change without notice
ad9736/ad9735/ad9734 preliminary technical data rev. prj | page 4 of 42 digital specifications 1 (vdda33 = vddd33 = 3.3 v, vdda18 = vddd18 = vddc lk = 1.8 v, maximum sa mple rate, fs = 20ma, 1x mode, 25 ohm 1% balanced load, unless otherwise noted) ad9736,35,34 parameter temp test level min typ max unit input voltage range, via or vib 825 1575 mv input differential threshold -100 100 mv input differential hysteresis 20 mv receiver differential in put impedance 80 120 ? lvds input rate 1200 msps lvds data inputs (db[13:0]+, db[13:0]-) db+ = via, db- = vib lvds data bit error rate tbd err/bit input voltage range, via or vib 825 1575 mv input differential threshold -100 100 mv input differential hysteresis 20 mv receiver differential in put impedance 80 120 ? lvds clock input (dataclk_in+, dataclk_in-) dataclk+ = via, dataclk- = vib maximum clock rate 600 mhz output voltage high, voa or vob 1375 mv output voltage low, voa or vob 1025 mv output differential voltage 150 200 250 mv output offset voltage 1150 1250 mv output impedance, si ngle ended 80 100 120 ? ro mismatch between a & b 10 % change in |vod| between 0 and 1 25 mv change in vos between 0 and 1 25 mv output current C driver shorted to ground 20 ma output current C drivers shorted together 4 ma power-off output leakage tbd ma lvds clock output (dataclk_out+, dataclk_ out-) dataclk_out+ = voa, dataclk_out- = vob 100 ohm termination maximum clock rate 600 mhz differential peak -to-peak voltage 800 mv common mode voltage 400 mv dac clock input (clk+, clk-) maximum clock rate 1200 mhz maximum clock rate (sclk, 1/t sclk ) 20 mhz minimum pulse width high, t pwh 20 ns minimum pulse width low, t pwl 20 ns minimum sdio and csb to sclk setup, t ds 10 ns minimum sclk to sdio hold, t dh 5 ns maximum sclk to valid sdio and sdo, t dv 20 ns serial peripheral interface minimum sclk to invalid sdio and sdo, t dnv 5 ns table 2: digital specifications 1 lvds drivers and receivers are co mpliant to the ieee-1596 reduced range link, un less otherwise noted
preliminary technical data ad9736/ad9735/ad9734 rev. prj | page 5 of 42 ac specifications (vdda33 = vddd33 = 3.3 v, vdda18 = vddd18 = vddc lk = 1.8 v, maximum sa mple rate, fs = 20ma, 1x mode, 25 ohm 1% balanced load, unless otherwise noted) ad9736 ad9735 ad9734 parameter temp test level min typ max min typ max min typ max unit maximum update rate 1200 1200 1200 msps output settling time (tst) (to 0.025%) tbd tbd tbd ns output rise time (10% to 90%) tbd tbd tbd ns output fall time (90% to 10%) tbd tbd tbd ns dynamic performance output noise (ioutfs=20ma) tbd tbd tbd pa/rthz f dac = 1200 msps, f out = 50 mhz 80 dbc f dac = 1200 msps, f out = 100 mhz 77 dbc f dac = 1200 msps, f out = 316 mhz 63 dbc spurious free dynamic range (sfdr) f dac = 1200 msps, f out = 550 mhz 55 dbc f dac = 1200 msps, f out = 50 mhz 85 dbc f dac = 1200 msps, f out = 100 mhz 84 dbc f dac = 1200 msps, f out = 316 mhz 74 dbc two tone intermodulati on distortion (imd) f dac = 1200 msps, f out = 550 mhz 65 dbc f dac = 1200 msps, f out = 50 mhz -165 dbm/hz f dac = 1200 msps, f out = 100 mhz -164 dbm/hz f dac = 1200 msps, f out = 316 mhz -158 dbm/hz noise spectral density (nsd) f dac = 1200 msps, f out = 550 mhz -155 dbm/hz table 3: ac specifications explanation of test levels test level i 100% production tested. ii 100% production tested at +25 c and guaranteed by design and charac terization at specified temperatures. iii sample tested only iv parameter is guaranteed by de sign and characterization testing. v parameter is a typical value only. vi 100% production tested at +25 c and guaranteed by design and characteriz ation for industrial temperature range.
ad9736/ad9735/ad9734 preliminary technical data rev. prj | page 6 of 42 pin function descriptions pin no. name description a1, a2, a3, b1, b2, b3, c1, c2, c3, d2, d3 vddc 1.8v, clock supply a4, a5, a6, a9, a10, a11, b4, b5, b6, b9, b10, b11, c4, c5, c6, c9, c10, c11, d4, d5, d6, d9, d10, d11 vssa analog supply ground a7, b7, c7, d7 ioutb dac negative output, 10ma to 30ma full scale output current a8, b8, c8, d8 iouta dac positive output, 10ma to 30ma full scale output current a12, a13, b12, b13, c12, c13, d12, d13 vdda 3.3v analog supply a14, k1 dnc do not connect b14 i120 nominal 1.2v reference tied to analog ground via 10kohm resistor to generate a 120ua reference current c14 vref bandgap voltage reference i/o, tie to an alog ground via 1nf capacitor, output impedance approximately 5kohms d1, e2, e3, e4, f2, f3, f4, g1, g2, g3, g4 vssc clock supply ground d14 iptat factory test, output current proportional to absolute temperature, approximately 10ua at 25c with approximately 20na/c slope e1, f1 clk-, clk+ negative, positive dac clock input (dacclk) e11, e12, f11, f12, g11, g12 vssa analog supply ground shield e13 irq / unsigned if pin_mode = 0, irq: active low open-dra in interrupt request output, pull up to vdd3.3 with 10kohm resistor if pin_mode = 1, unsigned: digital input pin where 0 = twos complement input data format, 1 = unsigned e14 reset / pd if pin_mode = 0, reset: 1 resets the ad9736 if pin_mode = 1, pd: 1 puts the ad9736 in the power down state f13 csb / 2x see spi and pin mode sections for pin description f14 sdio / fifo see spi and pin mode sections for pin description g13 sclk / fsc0 see spi and pin mode sections for pin description g14 sdo / fsc1 see spi and pin mode sections for pin description h1, h2, h3, h4, h11, h12, h13, h14, j1, j2, j3, j4, j11, j12, j13, j14 vdd 1.8v digital supply k2, k3, k4, k11, k12, l2, l3, l4, l5, l6, l9, l10, l11, l12, m3, m4, m5, m6, m9, m10, m11, m12 vss digital supply ground k13, k14 db<13> -, + negative, positive data input bit 13 (msb), reduced swing lvds l1 pin_mode 0, spi mode, spi enabled 1, pin mode, spi disabled, direct pin control l7, l8, m7, m8, n7, n8, p7, p8 vdd33 3.3v digital supply l13, l14 db<12> -, + negative, positive data input bit 12, reduced swing lvds m2, m1 db<0> -, + negative, positive data input bit 0 (lsb), reduced swing lvds m13, m14 db<11> -, + negative, positive data input bit 11, reduced swing lvds n1, p1 db<1> -, + negative, positive data input bit 1, reduced swing lvds n2, p2 db<2> -, + negative, positive data input bit 2, reduced swing lvds n3, p3 db<3> -, + negative, positive data input bit 3, reduced swing lvds n4, p4 db<4> -, + negative, positive data input bit 4, reduced swing lvds n5, p5 db<5> -, + negative, positive data input bit 5, reduced swing lvds n6, p6 dataclk_out -, + negative, positive output clock, reduced swing lvds n9, p9 dataclk_in -, + negative, positive data input clock, reduced swing lvds n10, p10 db<6> -, + negative, positive data input bit 6, reduced swing lvds n11, p11 db<7> -, + negative, positive data input bit 7, reduced swing lvds n12, p12 db<8> -, + negative, positive data input bit 8, reduced swing lvds n13, p13 db<9> -, + negative, positive data input bit 9, reduced swing lvds n14, p14 db<10> -, + negative, positive data input bit 10, reduced swing lvds
preliminary technical data ad9736/ad9735/ad9734 rev. prj | page 7 of 42 pin configuration 1234567891011121314 a b c d e f g h j k l m n p vdda, 3.3v, analog supply vssa, analog supply ground vssa, analog supply ground shield figure 2. ad9736 analog supply pins (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 a b c d e f g h j k l m n p vddc, 1.8v, clock supply vssc, clock supply ground figure 3. ad9736 clock supply pins (top view) 1234567891011121314 a b c d e f g h j k l m n p vdd, 1.8v digital supply vss digital supply ground vdd33, 3.3v digital supply figure 4. ad9736 digital supply pins (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 a b c d e f g h j k l m n p lvds13 (m s lvds11 lvds12 lvds0 (lsb) lvds10 lvds6 lvds7 lvds8 lvds9 lvds5 lvds1 lvds lvds3 lvds4 clkp clkn dclkp,n in lvdsclkp,n out figure 5. ad9736 digital lvds inputs, clock i/o (top view)
ad9736/ad9735/ad9734 preliminary technical data rev. prj | page 8 of 42 1 2 3 4 5 6 7 8 9 1011121314 a b c d e f g h j k l m n p ioutn ioutp i120 vref iptat pin_mode reset sdio sdo irq csb sclk pin_mode=0, spi enabled pd fifo fsc1 unsigned 2x fsco pin_mode=1, spi disabled figure 6. ad9736 analog i/o and spi control pins (top view)
preliminary technical data ad9736/ad9735/ad9734 rev. prj | page 9 of 42 package outline seating plane 0.25 min detail a 0.55 0.50 0.45 ball diameter 0.12 max coplanarity 0.80 bsc 10.40 bsc a b c d e f g h j k l m n p 14 13 12 11 10 8 7 6 3 2 1 95 4 1.00 0.85 a1 corner index area 1.40 max top view 12.00 bsc sq ball a1 indicator detail a compliant with jedec standards mo-205-ae. a 160-lead chip scale ball grid array [cspbga] (bc-160) dimensions shown in millimeters bottom view figure 7. ad9736 bga package outline drawing esd caution esd (electrostatic discharge) sensitive device. electrosta tic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although this product features proprietary esd protection circuitry, permanent damage may occur on de vices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to av oid performance degradation or loss of functionality. ordering guide model temperature range description ad9736bbc -40 c to +85 c (ambient) 160-lead chip scale bga AD9736-EB 25c (ambient) evaluation board table 4: ordering guide
ad9736/ad9735/ad9734 preliminary technical data rev. prj | page 10 of 42 typical performance characteristics -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 0 2048 4096 6144 8192 10240 12288 14336 16384 code error - lsb figure 8. ad9736, typical inl -0.7 -0.5 -0.3 -0.1 0.1 0.3 0.5 0 2048 4096 6144 8192 10240 12288 14336 16384 code error - lsb figure 9. ad9736, typical dnl 3rd order imd with respect to fout (20ma fs) 50 55 60 65 70 75 80 85 90 0 50 100 150 200 250 300 350 400 450 500 550 600 fout - [mhz] imd - [dbc] 800msps 1gsps 1.2gsps figure 10. ad9736, 3 rd order imd vs. fout and sample rate
preliminary technical data ad9736/ad9735/ad9734 rev. prj | page 11 of 42 nsd comparison with 1-tone and 8-tones at 1.2gsps -170 -168 -166 -164 -162 -160 -158 -156 -154 -152 -150 0 100 200 300 400 500 600 700 fout - mhz nsd - dbm/hz 1 tone 8 tones figure 11. ad9736, noise spectral density (nsd) vs. fout at 1.2gsps in- band sfdr with respect to fout (20ma fs) 50 55 60 65 70 75 80 85 90 0 50 100 150 200 250 300 350 400 450 500 550 600 fout - [mhz] sfdr - [dbc] 800msps 1gsps 1.2gsps figure 12. ad9736, in band sfdr vs. fout and sample rate
ad9736/ad9735/ad9734 preliminary technical data rev. prj | page 12 of 42 figure 13. ad9736, wcdma carrier at 134.83mhz, fdata=491.52msps figure 14. ad9735, wcdma carrier at 134.83mhz, fdata=491.52msps figure 15. ad9734, wcdma carrier at 134.83mhz, fdata=491.52msps
preliminary technical data ad9736/ad9735/ad9734 rev. prj | page 13 of 42 ad9736 power consumption 1x mode with respect to clock speed 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0 250 500 750 1000 1250 1500 fclk- mhz power - w vddd_1.8 vddd_33 vdda_1.8 vdda_3.3 total figure 16. ad9736 power vs. clock frequency ad9736 power consumption 2x mode with respect to clock speed 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0 250 500 750 1000 1250 1500 fclk- mhz power - w vddd_1.8 vddd_33 vdda_1.8 vdda_3.3 total figure 17. ad9736 power vs. clock frequency in 2x mode
ad9736/ad9735/ad9734 preliminary technical data rev. prj | page 14 of 42 spi register map adr dec adr hex register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default (hex) pin mode (hex) 0 00 mode sdio_dir lsbfirst reset long_ins 2x mode fifo mode datafrmt pd 00 00 1 01 irq lvds sync cross resvd ie_lvds ie_sync ie_cross resvd 00 00 2 02 fsc_1 sleep fsc<9> fsc<8> 02 02 3 03 fsc_2 fsc<7> fsc<6> fsc<5> fsc<4> fs c<3> fsc<2> fsc<1> fsc<0> 00 00 4 04 lvds_cnt1 msd<3> msd<2> msd<1> msd<0> mh d<3> mhd<2> mhd<1> mhd<0> 00 00 5 05 lvds_cnt2 sd<3> sd<2> sd<1> sd<0> lchange err_hi err_lo check 00 00 6 06 lvds_cnt3 lsurv lauto lflt<3> lflt<2> lflt< 1> lflt<0> ltrh<1> ltrh<0> 00 00 7 07 sync_cnt1 fifostat3 fifostat2 fifostat1 fifostat0 valid schange phof<1> phof<0> 00 00 8 08 sync_cnt2 ssurv sauto sflt<3> sflt<2> sflt<1> sflt<0> resvd strh<0> 00 00 9 09 reserved 10 0a reserved 11 0b reserved 12 0c reserved 13 0d reserved 14 0e ana_cnt1 msel<1> msel<0> trmbg< 2> trmbg<1> trmbg<0> c0 c0 15 0f ana_cnt2 hdrm<7> hdrm<6> hdrm<5> hdrm<4> hdrm<3> hdrm<2> hdrm<1> hdrm<0> ca ca 16 10 reserved 17 11 bist_cnt sel<1> sel<0> sig_read lvds_en sync_en clear 00 00 18 12 bist<7:0> 19 13 bist<15:8> 20 14 bist<23:16> 21 15 bist<31:24> 22 16 cclk_div resvd resvd resvd resvd ccd<3> ccd<2> ccd<1> ccd<0> 00 00 31 1f version ver<5> ver<4> ver<3> ver<2> ver<1> ver<0> res10 res12 note: write 0 to unspecified or reserved bit locations. reading these bits will return unknown values. table 5. spi register map
preliminary technical data ad9736/ad9735/ad9734 rev. prj | page 15 of 42 spi register descriptions reg 00 -> mode reading reg 00 returns previously written values for all defined register bits unless otherwise noted. reset value in bold text. adr name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x00 mode sdio_dir lsb/msb reset long_ins 2x mode fifo mode datafrmt pd sdio_dir : write -> 0 , input only per spi standard 1, bidirectional per spi standard lsbfirst : write -> 0 , msb first per spi standard 1, lsb first per spi standard note: only change lsb/msb order in single byte instructions to avoid erratic behavior due to bit order errors reset : write-> 0 , execute software reset of spi and controllers, reload default register values except registers 0x00 and 0x04 1, set software reset prior to writing 0 to execute the software reset long_ins : write -> 0 , short (single-byte) instruction word 1, long (two-byte) instruction word, not necessary since the maximum internal address is reg31 (0x1f) 2x_mode : write -> 0 , disable 2x interpolation filter 1, enable 2x interpolation filter fifo_mode : write -> 0 , disable fifo synchronization 1, enable fifo synchronization datafrmt : write -> 0 , signed input data with midscale = 0x0000 1, unsigned input data with midscale = 0x2000 pd : write -> 0 , enable lvds receiver, dac and clock circuitry 1, power down lvds receiver, dac and clock circuitry reg 01 -> interrupt request (irq) reading reg 01 returns previously written values for all defined register bits unless otherwise noted. reset value in bold text. adr name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x01 irq lvds sync cross resvd ie_lvds ie_sync ie_cross resvd lvds : write -> dont care : read -> 0, no active lvds receiver interrupt 1, interrupt in lvds receiver occurred sync : write -> dont care : read -> 0, no active sync logic interrupt 1, interrupt in sync logic occurred cross : write -> dont care : read -> 0, no active cross logic interrupt 1, interrupt in cross logic occurred ie_lvds : write -> 0 , reset lvds receiver interrupt and disable future lvds receiver interrupts 1, enable lvds receiver interrupt to activate irq pin ie_sync : write -> 0 , reset sync logic interrupt and di sable future sync logic interrupts 1, enable sync logic interrupt to activate irq pin ie_cross : write -> 0 , reset cross logic interrupt and disable future cross logic interrupts 1, enable cross logic interrupt to activate irq pin
ad9736/ad9735/ad9734 preliminary technical data rev. prj | page 16 of 42 reg 02, 03 -> full scale current (fsc) reading reg 02 & 03 return previously written values for all defined register bits unless otherwise noted. reset value in bold text. adr name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x02 fsc_1 sleep fsc<9> fsc<8> 0x03 fsc_2 fsc<7> fsc<6> fsc<5> fsc< 4> fsc<3> fsc<2> fsc<1> fsc<0> sleep : write -> 0 , enable dac output 1, set dac output current to 0ma fsc<9:0> : write -> 0x000, 10ma full scal e output current 0x200 , 20ma full scale output current note: iout = (72 + 192 * ( fsc<9:0> / 1024 ) ) * i120 0x3ff, 30ma full scale output current where i120 = vref / r120u, for example 1.2v / 10k = 120ua reg 04, 05, 06 -> lvds controller (lvds_cnt) reading reg 04, 05 & 06 return previously written values for all defined register bits unless otherwise noted. reset value in bold text. adr name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x04 lvds_cnt1 msd<3> msd<2> msd<1> ms d<0> mhd<3> mhd<2> mhd<1> mhd<0> 0x05 lvds_cnt2 sd<3> sd<2> sd<1> sd<0> lchange err_hi err_lo check 0x06 lvds_cnt3 lsurv lauto lflt<3> lflt<2> lflt<1> lflt<0> ltrh<1> ltrh<0> msd<3:0> : write -> 0x0 , set setup delay for the measurement system : read -> if ( lauto == 1) the latest measured value for the setup delay if ( lauto == 0) read back of the last spi write to this bit mhd<3:0> : write -> 0x0 , set hold delay for the measurement system : read -> if ( lauto == 1) the latest measured value for the hold delay if ( lauto == 0) read back of the last spi write to this bit sd<3:0> : write-> 0x0 , set sample delay : read -> if ( lauto == 1) the result of a measurement cycle is stored in this register if ( lauto == 0) read back of the last spi write to this bit lchange : read -> 0, no change from previous measurement 1, change in value from the previous measurement note: the average filter and the threshold detection are not applied to this bit err_hi : read -> one of the 15 lvds inputs is above the input voltage limits of the ieee reduce link spec. err_lo : read -> one of the 15 lvds inputs is below the input voltage limits of the ieee reduced link spec. check : read -> 0, phase measurement C sampling in the previous or following data cycle 1, phase measurement C sampling in the correct data cycle lsurv : write -> 0 , the controller stops after completion of the current measurement cycle 1, continuous measurements are taken and an interrupt is issu ed if the clock alignment drifts beyond the threshold value lauto : write -> 0 , sample delay is not automatically updated 1, continuously starts measurement cycles and updates the sample delay according to the measurement note: lsurv (reg06 bit 7) must be set to 1 and the lv ds irq (reg01 bit 3) must be set to 0 for auto mode lflt<3:0> : write -> 0x0 , average filter length, delay = delay + delta delay / 2^ lflt<3:0>, values greater than 12 (0x0c) are clipped to 12
preliminary technical data ad9736/ad9735/ad9734 rev. prj | page 17 of 42 ltrh<2:0> : : write -> 000 , set auto update threshold values reg 07, 08 -> sync controller (sync_cnt) reading reg 07 & 08 return previously written values for all defined register bits unless otherwise noted. reset value in bold text. adr name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x07 sync_cnt1 fifostat3 fifostat2 fifostat1 fifostat0 valid schange phof<1> phof<0> 0x08 sync_cnt2 ssurv sauto sflt<3> sflt<2> sflt<1> sflt<0> resvd strh<0> fifostat<2:0> : read -> position of fifo read counter, range from 0 to 7 fifostat<3> : read -> 0, sync logic ok 1, error in sync logic valid : read -> 0, fifostat<3:0> is not valid yet 1, fifostat<3:0> is valid after a reset schange : read -> 0, no change in fifostat<3:0> 1, fifostat<3:0> has changed since the previous measurement cycle when ssurv = 1 (surveillance mode active) phof<1:0> : write -> 00 , change the readout counter : read -> current setting of the readout counter (phof<1:0>) in surveillance mode (ssurv = 1) after an interrupt current calculated optimal readout counter value in auto mode (sauto = 1) ssurv : write -> 0 , the controller stops after completion of the current measurement cycle 1, continuous measurements are taken and an interrupt is issued if the readout counter drifts beyond the threshold value sauto : write -> 0 , readout counter (phof<3:0>) is not automatically updated 1, continuously starts measurement cycles and upda tes the readout counter acco rding to the measurement note: ssurv (reg08 bit 7) must be set to 1 and the sy nc irq (reg01 bit 2) must be set to 0 for auto mode sflt<3:0> : write -> 0x0 , average filter length, fifostat = fifostat + delta fifostat / 2 ^ sflt<3:0>, values greater than 12 (0x0c) are clipped to 12 strh<0> : write -> 0 , if fifostat<2:0> = 0 | 7, generate a sync interrupt 1, if fifostat<2:0> = 0 | 1 | 6 | 7, generate a sync interrupt reg 14, 15 -> analog control (ana_cnt) reading reg 14 & 15 return previously written values for all defined register bits unless otherwise noted. reset value in bold text. adr name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0e ana_cnt1 msel<1> msel<0> trmbg<2> trmbg<1> trmbg<0> 0x0f ana_cnt2 hdrm<7> hdrm<6> hdrm<5> hdrm<4> hdrm<3> hdrm<2> hdrm<1> hdrm<0> msel<1:0> : write -> 00, mirror roll off frequency control = bypass 01, mirror roll off frequency control = narrowest bandwidth 10, mirror roll off frequency control = medium bandwidth 11 , mirror roll off frequency control = widest bandwidth note: see plot in the applications section trmbg<2:0> : write -> 000 , bandgap temperature characteristic trim note: see plot in the applications section hdrm<7:0> : write -> 0xca , output stack headroom control hdrm<7:4> set reference offset from vdd3v (vcas centering) hdrm<3:0> set overdrive (current density) trim (temperature tracking) note: set to 0xca for optimum performance
ad9736/ad9735/ad9734 preliminary technical data rev. prj | page 18 of 42 reg 17, 18, 19, 20, 21 -> built-in self test control (bist_cnt) reading reg17, 18, 19, 20 & 21 return previously written values for all defined register bits unless otherwise noted. reset val ue in bold text. adr name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x11 bist_cnt sel<1> sel<0> sig_read lvds_en sync_en clear 0x12 bist<7:0> bist<7> bist<6> bist<5> bi st<4> bist<3> bist<2 > bist<1> bist<0> 0x13 bist<15:8> bist<15> bist<14> bist<13> bist<12> bist<11> bist<10> bist<9> bist<8> 0x14 bist<23:16> bist<23> bist<22> bist<21> bi st<20> bist<19> bist<18> bist<17> bist<16> 0x15 bist<31:24> bist<31> bist<30> bist<29> bi st<28> bist<27> bist<26> bist<25> bist<24> sel<1:0> : write -> 00, write result of the lvds phase 1 bist to bist<31:0> 01, write result of the lvds phase 2 bist to bist<31:0> 10, write result of the sync phase 1 bist to bist<31:0> 11, write result of the sync phase 2 bist to bist<31:0> sig_read : write -> 0, no action 1, enable bist signature readback lvds_en : write-> 0, no action 1, enable lvds bist sync_en : write -> 0, no action 1, enable sync bist clear : write -> 0, no action 1, clear all bist registers bist<31:0> : read -> results of the built-in self test reg 22 -> controller clock pre-divider (cclk_div) reading reg 22 returns previously written values for all defined register bits unless otherwise noted. reset value in bold text. adr name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x16 cclk_div resvd resvd resvd resvd ccd<3> ccd<2> ccd<1> ccd<0> ccd<3:0> : write -> 0x0 , controller clock = dacclk / 16 0x1, controller clock = dacclk / 32 0x2, controller clock = dacclk / 64 0xf, controller clock = dacclk / 524288 note: the 100mhz to 1.2ghz dacclk must be divided to less than 10mhz for correct operation. ccd<3:0> must be programmed to divide the dacclk so that this relationship is not violated. controller clock = dacclk / ( 2 ^ ( ccd<3:0> + 4 )) reg 31 -> version reading reg 31 returns previously written values for all defined register bits unless otherwise noted. reset value in bold text. adr name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x1f version ver<5> ver<4> ver<3> ver<2> ver<1> ver<0> res10 res12 ver<5:0> : read -> version number (part id), 00001, revision 1, initial release res10 (msb) res12 (lsb) : read -> 00, 14-bit dac 01, 12-bit dac 10, 10-bit dac
preliminary technical data ad9736/ad9735/ad9734 rev. prj | page 19 of 42 general description the ad9736/35/34 are 14/12/10-bit dacs which run at an update rate up to 1.2gsps. input data can be accepted up to the full 1.2gsps rate or a 2x interpolation filter may be enabled (2x mode) allowing full-speed operation with a 600msps input data rate. data and dataclk_in inputs are parallel lvds meeting the ieee reduced swing lvds specifications with the exception of input hysteresis. the dataclk_in input runs at one half the input data rate in a double data rate (ddr) format. each edge of dataclk_in is used to transfer data into the ad9736 as shown in figure 25. the dacclk (pins e1, f1) directly drives the dac core to minimize clock jitter. it is also divided by two (1x and 2x mode) then output as the dataclk_out. the dataclk_out signal is used to clock the data source. the dac expects ddr lvds data (db<13:0>) aligned with the ddr input clock (dataclk_in) from a circuit similar to the one shown in figure 35. clock relationships are shown in table 6. mode dacclk dataclk out dataclk in data 1x 1.2ghz 600mhz 600mhz 1.2gsps 2x 1.2ghz 600mhz 300mhz 600msps table 6. ad9736 clock relationships maintaining correct alignment of data and clock is a common challenge with high-speed dacs, complicated by changes in temperature and other operating conditions. the ad9736 simplifies this high-speed data capture problem with two adaptive closed-loop timing controllers. one timing controller manages the lvds data and data clock alignment (lvds controller) and the other manages the lvds data and dacclk alignment (sync controller). the lvds controller locates the data transitions and delays the dataclk_in so that its transition is in the center of the valid data window. the sync controller manages the fifo that moves data from the lvds dataclk_in domain to the dacclk domain. both controllers can be operated in manual mode under external processor control, surveillance mode where error conditions generate external interrupts or automatic mode where errors are automatically corrected. the lvds and sync controllers include moving average filtering for noise immunity and variable thresholds to control their activity. normally the controllers can be set to run in automatic mode and they will make any necessary adjustments without dropping or duplicating samples sent to the dac. both controllers require initial calibration prior to entering automatic update mode. control of the ad9736 functions is via the serially programmed registers listed in table 5. serial peripheral interface the ad9736 serial port is a flexible, synchronous serial communications port allowing easy interface to many industry- standard microcontrollers and microprocessors. the serial i/o is compatible with most synchronous transfer formats, including both the motorola spi? and intel? ssr protocols. the interface allows read/write access to all registers that configure the ad9736. single or multiple byte transfers are supported, as well as msb first or lsb first transfer formats. the ad9736s serial interface port can be configured as a single pin i/o (sdio) or two unidirectional pins for in/out (sdio/sdo). figure 18. ad9736 spi port the ad9736 may optionally be configured via external pins rather than the serial interface. when the pin_mode input (pin l1) is high the serial interface is disabled and its pins are reassigned for direct control of the dac. specific functionality is described in the pin mode section. general operation of the serial interface there are two phases to a communication cycle with the ad9736. phase 1 is the instruction cycle, which is the writing of an instruction byte into the ad9736, coincident with the first eight sclk rising edges. the instruction byte provides the ad9736 serial port controller with information regarding the data transfer cycle, which is phase 2 of the communication cycle. the phase 1 instruction byte defines whether the upcoming data transfer is read or write, the number of bytes in the data transfer, and the starting register address for the first byte of the data transfer. the first eight sclk rising edges of each communication cycle are used to write the instruction byte into the ad9736. the remaining sclk edges are for phase 2 of the communication cycle. phase 2 is the actual data transfer between the ad9736 and the system controller. phase 2 of the communication cycle is a transfer of 1, 2, 3, or 4 data bytes as determined by the instruction byte. using one multibyte transfer is the preferred method. single byte data transfers are useful to reduce cpu overhead when register access requires one byte only. registers change immediately upon writing to the last bit of each transfer byte. csb can be raised after each sequence of 8 bits (except the last byte) to stall the bus. the serial transfer will resume when csb is lowered. stalling on non-byte boundaries will reset the spi. sdo (pin g14) sdio (pin f14) sclk (pin g13) csb (pin f13) ad9736 spi port
ad9736/ad9735/ad9734 preliminary technical data rev. prj | page 20 of 42 short instruction mode (8-bit instruction) the short instruction byte is shown in table 7. msb lsb i7 i6 i5 i4 i3 i2 i1 i0 r/w n1 n0 a4 a3 a2 a1 a0 table 7. spi instruction byte r/w , bit 7 of the instruction byte, determines whether a read or a write data transfer will occur after the instruction byte write. logic high indicates read operation. logic 0 indicates a write operation. n1, n0 , bits 6 and 5 of the instruction byte, determine the number of bytes to be transferred during the data transfer cycle. the bit decodes are shown in table 8. a4, a3, a2, a1, a0 , bits 4, 3, 2, 1, 0 of the instruction byte, determine which register is accessed during the data transfer portion of the communications cycle. for multibyte transfers, this address is the starting byte address. the remaining register addresses are generated by the ad9736 based on the lsbfirst bit (reg00, bit 6). n1 n2 description 0 0 transfer 1 byte 0 1 transfer 2 bytes 1 0 transfer 3 bytes 1 1 transfer 4 bytes table 8. byte transfer count long instruction mode (16-bit instruction) the long instruction bytes are shown in table 7. msb lsb i15 i14 i13 i12 i11 i10 i9 i8 r/w n1 n0 a12 a11 a10 a9 a8 i7 i6 i5 i4 i3 i2 i1 i0 a7 a6 a5 a4 a3 a2 a1 a0 table 9. spi instruction byte if long_ins = 1 (reg00, bit 4) the instruction byte is extended to two bytes where the second byte provides an additional 8 bits of address information. addresses 0x00 C 0x1f are equivalent in short and long instruction modes. the ad9736 does not use any addresses greater than 31 (0x1f) so always set long_ins = 0. serial interface port pin descriptions sclkserial clock . the serial clock pin is used to synchronize data to and from the ad9736 and to run the internal state machines. sclks maximum frequency is 20 mhz. all data input to the ad9736 is registered on the rising edge of sclk. all data is driven out of the ad9736 on the rising edge of sclk. csbchip select . active low input starts and gates a communication cycle. it allows more than one device to be used on the same serial communications lines. the sdo and sdio pins will go to a high impedance state when this input is high. chip select should stay low during the entire communication cycle. sdioserial data i/o . data is always written into the ad9736 on this pin. however, this pin can be used as a bidirectional data line. the configuration of this pin is controlled by sdio_dir at reg00, bit 7. the default is logic 0, which configures the sdio pin as unidirectional. sdoserial data out . data is read from this pin for protocols that use separate lines for transmitting and receiving data. in the case where the ad9736 operates in a single bidirectional i/o mode, this pin does not output data and is set to a high impedance stat e. msb/lsb transfers the ad9736 serial port can support both most significant bit (msb) first or least significant bit (lsb) first data formats. this functionality is controlled by lsbfirst at reg00, bit 6. the default is msb first (lsbfirst = 0). when lsbfirst = 0 (msb first) the instruction and data bytes must be written from most significant bit to least significant bit. multibyte data transfers in msb first format start with an instruction byte that includes the register address of the most significant data byte. subsequent data bytes should follow in order from high address to low address. in msb first mode, the serial port internal byte address generator decrements for each data byte of the multibyte communication cycle. when lsbfirst = 1 (lsb first) the instruction and data bytes must be written from least significant bit to most significant bit. multibyte data transfers in lsb first format start with an instruction byte that includes the register address of the least significant data byte followed by multiple data bytes. the serial port internal byte address generator increments for each byte of the multibyte communication cycle. the ad9736 serial port controller data address will decrement from the data address written toward 0x00 for multibyte i/o operations if the msb first mode is active. the serial port controller address will increment from the data address written toward 0x1f for multibyte i/o operations if the lsb first mode is active. notes on serial port operation the ad9736 serial port configuration is controlled by reg00, bits 4, 5, 6 and 7. it is important to note that the configuration changes immediately upon writing to the last bit of the register. for multibyte transfers, writing to this register may occur during the middle of communication cycle. care must be taken to compensate for this new configuration for the remaining bytes of the current communication cycle. the same considerations apply to setting the software reset, reset (reg00, bit 5). all registers are set to their default values except reg00 and reg04 which remain unchanged. use of only single byte transfers when changing serial port
preliminary technical data ad9736/ad9735/ad9734 rev. prj | page 21 of 42 configurations or initiating a software reset is highly recommended. in the event of unexpected programming sequences the ad9736 spi may become inaccessible. for example, if user code inadvertently changes the long_ins bit or lsbfirst bit the following bits may have unexpected results. the spi can be returned to a known state by writing an incomplete byte (1-7 bits) of all zeroes followed by three bytes of 0x00. this will return to msb first short instructions (reg00 = 0x00) so the device may be reinitialized. r/wn0n1 a0a1 a2a3a4d7d6 n d5 n d0 0 d1 0 d2 0 d3 0 d7 d6 n d5 n d0 0 d1 0 d2 0 d3 0 instruction cycle data transfer cycle csb sclk sdio sdo figure 19. serial register interface timing msb first instruction cycle data transfer cycle csb sclk sdio sdo a0 a1 a2 a3 a4 n1 n0 r/w d0 d1 0 d2 0 d7 n d6 n d5 n d4 n d0d1 0 d2 0 d7 n d6 n d5 n d4 n figure 20. serial register interface timing lsb first instruction bit 6 instruction bit 7 csb sclk sdio t ds t ds t dh t pwh t pwl t sclk 03152-prd-006 figure 21. timing diagram for spi register write i1 i0 d7 d6 d5 t dv t dnv csb sclk sdio figure 22. timing diagram for spi register read after the last instruction bit is written to the sdio pin the driving signal must be set to a high impedance in time for the bus to turn around. the serial output data from the ad9736 will be enabled by the falling edge of sclk. this causes the first output data bit to be shorter than the remaining data bits as shown in figure 22. pin mode operation when the pin_mode input (pin l1) is set high, the spi port is disabled. the spi port pins are remapped as shown in table 10. the function of these pins is described in table 11. the remaining pin_mode register settings are shown in table 5, the spi register map. pin number pin_mode = 0 pin_mode = 1 e13 irq unsigned f13 csb 2x g13 sclk fsc0 e14 reset pd f14 sdio fifo g14 sdo fsc1 table 10. spi_mode vs. pin_mode inputs pin function unsigned 0, twos complement input data format 1, unsigned input data format 2x 0, interpolation disabled 1, interpolation = 2x enabled fsc1, fsc0 00, sleep mode 01, 10ma full scale output current 10, 20ma full scale output current 11, 30ma full scale output current pd 0, chip enabled 1, chip in power down state fifo 0, input fifo disabled 1, input fifo enabled table 11. pin_mode input functions care must be taken when using pin_mode since only the control bits shown in table 11 can be changed. if the remaining register default values are not suitable for the desired operation pin_mode cannot be used.
ad9736/ad9735/ad9734 preliminary technical data rev. prj | page 22 of 42 ad9736 data interface controllers there are 2 internal controllers that can be utilized in the operation of the ad9736. the first controller helps maintain optimum lvds data sampling and the second controller helps maintain optimum synchronization between the dacclk and the incoming data. the lvds controller is responsible for optimizing the sampling of the data from the lvds bus (db13:0) while the sync controller resolves timing problems between the dac_clk (clk+, clk-) and the dataclk. a block diagram of these controllers is shown in figure 23. the controllers are clocked with a divided down version of the dac_clk. the divide ratio is set utilizing the controller clock predivider bits (ccd<3:0>) located at reg22 bits 3:0 to generate the controller clock as follows: controller clock = dac_clk / ( 2 ^ ( ccd<3 :0> + 4 )) note : the controller clock may not exceed 10mhz for correct operation. until ccd<3:0> has been properly programmed to meet this requirement the dac output may not be stable. the lvds and sync controllers can be independently operated in 3 different modes via spi port reg06 and reg08. 1. manual mode 2. surveillance mode 3. auto mode in manual mode all of the timing measurements and updates are externally controlled via the spi. in surveillance mode each controller takes measurements and calculates a new optimal value continuously. the result of the measurement can be passed through an averaging filter before evaluating the results for increased noise immunity. the filtered result is compared to a threshold value set via reg06 and reg08 of the spi port. if the error is greater then the threshold, an interrupt is triggered and the controller stops. reg01 of the spi port controls the interrupts with bits 3 and 2 enabling the respective interrupts and bits 7 and 6 indicating the respective controllers interrupt. if an interrupt is enabled it will also activate the ad9736s irq pin. in order to clear an interrupt the interrupt enable bit of the respective controller must be set to a zero for at least one controller clock cycle (controller clock < 10mhz). auto mode is almost identical to surveillance mode. instead of triggering an interrupt and stopping the controller, the controller automatically updates its settings to the newly calculated optimal value and continues to run. figure 23.ad9736 internal synchronization engine data source i.e. fpga lvds sample logic fifo sync logic dac dacclk dataclk_out db<13:0> dataclk_in clk control lvds controller sync controller data source i.e. fpga lvds sample logic fifo sync logic dac dacclk dataclk_out db<13:0> dataclk_in clk control lvds controller sync controller
preliminary technical data ad9736/ad9735/ad9734 rev. prj | page 23 of 42 ad9736 lvds sample logic a simplified diagram of the ad9736 lvds data sampling engine is shown in figure 24, with the timing relationships shown in figure 25. the incoming lvds data is latched by the data sampling signal (dss) which is derived from dataclk_in. the lvds controller delays dataclk_in to create the data sampling signal (dss) which is adjusted to sample the lvds data in the center of the valid data window. the skew between the dataclk_in and the lvds data bits (db<13:0>) must be minimal (t1 and t2 in figure 25) for proper operation. therefore, it is recommended that the dataclk_in be generated in the same manner as the lvds data bits (db<13:0>) with the same driver and data lines (i.e. it should just be another lvds data bit running a constant 01010101 sequence, as shown in figure 35). figure 24. ad9736 internal lvds data sampling logic lvds sample logic calibration the internal data sampling signal delay must be calibrated to optimize the data sample timing. once calibrated, the ad9736 can generate an irq or automatically correct its timing if temperature or voltage variations change the timing too much. this calibration is done by using the delayed clock sampling signal (css) to sample the delayed clock signal (dcs). the lvds sampling logic can find the edges of the dataclk_in signal and from this measurement the center of the valid data window can be located. the internal delay line which derives the delayed data sampling signal (dss) from dataclk_in is controlled by sd3:0 (reg05, bits 7:4) while the delayed clock signal (dcs) is controlled by msd3:0 (reg04, bits 7:4) and the clock sampling signal (css) is controlled by mhd3:0 (reg04, bits 3:0). dataclk_in transitions must be time aligned with the lvds data (db<13:0>) transitions. this allows the clock sampling signal (css, derived from the dataclk_in), to find the valid data window of db<13:0> by locating the dataclk_in edges. the latching (rising) edge of css is initially placed using bits sd<3:0> and can then be shifted to the left using msd<3:0> and to the right using mhd<3:0>. when css samples the delayed clock signal (dcs) and the result is a 1, (which can be read back via the check bit at reg05, bit 0) then the sampling is occurring in the correct data cycle. in order to find the leading edge of the data cycle, increment msd (measured set-up delay) until check goes low. in order to find the trailing edge, increment mhd (measured hold delay) until check goes low. always set mhd = 0 when incrementing msd and vice-versa. note: the incremental units of sd, msd, and mhd are in units of real time, not fractions of a clock cycle. at this time, the delay from each increment of these bits has not been fully characterized. over process, voltage, and temperature, each increment may introduce between 25 and 100ps of delay with a nominal target of 80ps. operating the lvds controller in manual mode via the spi port the manual operation of the lvds controller allows the user to step through both the set-up and hold delays to calculate the optimal sampling delay (i.e. center of the data eye). with sd<3:0> and mhd<3:0> set to zero, increment the set-up time delay (msd<3:0>, reg04, bits 7:4) until the check bit (reg05, bit 0) goes low and record this value. this locates the leading dataclk_in (and data) transition as shown in figure 26. with sd<3:0> and msd<3:0> set to zero, increment the hold time delay (mhd<3:0>, reg04, bits 3:0) until the check bit (reg05 bit 0) goes low and record this value. this locates the trailing dataclk_in (and data) transition as shown in figure 27. once both dataclk_in edges are located the sample delay (sd<3:0>, reg05, bits 7:4) must be updated according to the following equation: sample delay = ( mhd C msd ) / 2 after updating sd<3:0>, verify that the sampling signal is in the middle of the valid data window by adjusting both mhd then msd with the new sample delay until the check bit goes low. the new mhd and msd values should be equal or within one unit delay if sd<3:0> was set correctly. note : the sample delay calibration just described should be performed prior to enabling surveillance mode or auto mode. lvds rx lvds rx ff sd<3:0> sample delay ff d1 d2 db<13:0> dataclk in data sampling signal ff msd<3:0> delay mhd<3:0> delay chec k clock sampling signal delayed clock signal
ad9736/ad9735/ad9734 preliminary technical data rev. prj | page 24 of 42 figure 25. ad9736 internal lvds data sampling logic timing figure 26. set-up delay measurement figure 27. hold delay measurement db13:0 dataclk_in data sampling signal d1 d2 t1 t2 sample delay prop delay to latch prop delay to latch db<13:0> dataclk_in css with mhd<3:0> = 0 dcs, delayed by msd<3:0> msd<3:0> = 0 1 2 3 4 5 set up time (ts) hold time (th) check = 1 1 1 1 1 0 sample delay , sd<3:0> css samples dcs check = 1 db<13:0> dataclk_in dcs with msd<3:0> = 0 mhd<3:0> = 0 1 2 3 4 5 check = 1 1 1 1 1 0 set up time (ts) hold time (th) sample delay, sd<3:0> css samples dcs css, delayed by mhd<3:0> check = 1
preliminary technical data ad9736/ad9735/ad9734 rev. prj | page 25 of 42 operating the lvds controller in surveillance and auto mode in surveillance mode, the controller searches for the edges of the data eye in the same manner as above in the manual mode of operation and triggers an interrupt if the clock sampling signal (css) has moved more than the threshold value set by lthr<1:0> (reg06, bits 1:0). there is an internal filter which averages the set-up and hold time measurements to filter out noise and glitches on the clock lines. average value = ( mhd C msd ) / 2 new average = average value + ( delta average / 2 ^ lflt<3:0> ) if an accumulating error in the average value causes it to exceed the threshold value (lthr<1:0>) an interrupt will be issued. the maximum allowable value for lflt<3:0> is 12. in surveillance mode, the ideal sampling point should first be found using manual mode and applied to the sample delay registers. the user should then set the threshold and filter values depending on how far the css signal is allowed to drift before an interrupt occurs. then set the surveillance bit high (reg06, bit 7) and monitor the interrupt signal either via the spi port read back (reg01, bit 3) or the irq pin. in auto mode, the same steps should be taken to set up the sample delay, threshold and filter length. in order to run the controller in auto mode both the lauto (reg06, bit 6) and lsurv (reg06, bit 7) bits need to be set to 1. in auto mode the lvds interrupt should be set low (reg01, bit 7) to allow the sample delay to be automatically updated if the threshold value is exceeded. ad9736 sync logic and controller a fifo structure is utilized to synchronize the data transfer between the dacclk and the dataclk_in clock domains. the sync controller writes data from db<13:0> into an eight word memory based on a cyclic write counter clocked by the clock sampling signal (css) which is a delayed version of dacclk_in. the data is read out of the memory based on a second cyclic read counter clocked by dacclk. the eight word deep fifo shown in figure 28 provides sufficient margin to maintain proper timing under most conditions. the sync logic is designed to prevent the read and write pointers from crossing. if the timing drifts far enough to require an update of the phase offset (phof<1:0>) two samples will be duplicated or dropped. figure 29 shows the timing diagram for the sync logic. sync logic and controller operation the relationship between the readout pointer and the write pointer will initially be unknown since the startup relationship between dacclk and dataclk_in is unknown. the sync logic measures the relative phase between the two counters with the zero detect block and the flip flop in figure 5 above. the relative phase is returned in fifostat<2:0> (reg07, bits 6:4) and sync logic errors are indicated by fifostat<3> (reg07, bit 7). if fifostat<2:0> returns a value of zero or seven it signifies that the memory is sampling in a critical state (read and write pointers are close to crossing). if the fifostat<2:0> returns a value of 3 or 4 it signifies the memory is sampling at the optimal state (read and write pointers are farthest apart). if fifostat<2:0> returns a critical value the pointer can be adjusted with the phase offset phof<1:0> (reg07, bits 1:0). due to the architecture of the fifo the phase offset can only adjust the read pointer in steps of two. operating in manual mode allow dacclk and dataclk_in to stabilize then enable fifo mode (reg00, bit 2). read fifostat<2:0> (reg07, bits 6:4) to determine if adjustment is needed. for example if fifostat<2:0> = 6 the timing is not yet critical but it is not optimal. to return to an optimal state (fifostat<2:0> = 4) the phof<1:0> (reg07, bits 1:0) needs to be set to 1. setting phof<1:0> = 1 effectively increments the read pointer by 2. this causes the write pointer value to be captured two clocks later decreasing fifostat<2:0> from 6 to 4. figure 28. sync logic block diagram 8 word memory dac<13:0> db<13:0> m0 m7 write counter read counter adder css dacclk phof<1:0> zd ff ff fifostat<2:0> 8 word memory dac<13:0> db<13:0> m0 m7 write counter read counter adder css dacclk phof<1:0> zd ff ff fifostat<2:0>
ad9736/ad9735/ad9734 preliminary technical data rev. prj | page 26 of 42 operation in surveillance and auto modes once fifostat<2:0> has been manually placed in an optimal state the ad9736 sync logic can be run in surveillance or auto mode. to start, turn on surveillance mode by setting ssurv = 1 (reg08, bit 7) then enable the sync interrupt (reg01, bit 2). if strh<0> = 0 (reg08, bit 0) an interrupt will occur if fifostat<2:0> = 0 or 7. if strh<0> = 1 (reg08, bit 0) an interrupt will occur if fifostat<2:0> = 0, 1, 6 or 7. the interrupt can be read at reg01, bit 6 at the ad9736 irq pin. to enter auto mode, complete the preceding steps then set sauto = 1 (reg09, bit 6). next set the sync interrupt = 0 (reg01, bit 2), to allow the phase offset (phof<1:0>) to be automatically updated if fifostat<2:0> violates the threshold value. the fifostat signal is filtered to improve noise immunity and reduce unnecessary phase offset updates. the filter operates with the following algorithm: fifostat = fifostat + delta fifostat / 2 ^ sflt<3:0> where 0 <= sflt<3:0> <= 12. values greater than 12 are set to 12. sample_hold sample_setup sample_delay external_delay intern al_delay b c d e f g h i j k m o l n p r q a a b c d e f g h i j k l m n o p q 0 1 2 3 4 5 6 7 0 1 2 3 a c e g i k m 4 5 6 7 0 1 2 3 4 5 6 7 4 0 4 4 4 a b c d e f g h i j k l m 5 6 7 0 1 b d f h j l 1 2 3 4 dacclk dataclk_out dataclk_in data_in css1 d1 css2 d2 write_ptr1 m0 m1 m2 m3 m4 m5 m6 m7 read_ptr1 fifostat dac_data figure 29. sync logic timing diagram safe zone error zone data a can be safely read from the fifo in the safe zone. in the error zone, the pointers may briefly overlap due to clock jitter or fifostat is set equal to the write pointer each time the read pointer changes from 7 to 0.
preliminary technical data ad9736/ad9735/ad9734 rev. prj | page 27 of 42 ad9736 digital built-in self test bist may be used to validate data transfer to the ad9736 in addition to final ate device verification. there are 4 bist signatures that can be read back using registers 18-21 based on the setting of the bist selection bits (reg17, bits 7:6) as shown in table 12. sel<1> sel<0> 1 - lvds phase 1 0 0 2 - lvds phase 2 0 1 3 - sync phase 1 1 0 4 - sync phase 2 1 1 table 12. bist selection bits the bist signature returned from the ad9736 will depend on the input data during the test. since the filters in the dac have memory, it is important to put the correct idle value on the data inputs to flush the memory prior to reading the bist signature. placing the idle value on the data inputs also allows the bist to be setup while the dac clock is running. the idle value should be all zeroes in unsigned mode (0x0000) and all zeroes except for the msb in twos complement mode (0x2000). the bist consists of two stages; the first stage is after the lvds receiver and the second stage is after the fifo stage. the first bist stage verifies correct sampling of the data from the lvds bus while the second bist stage verifies correct synchronization between the dac_clk domain and the data_clk domain. the bist vector is generated using 32 bit lfsr signature logic. since the internal architecture is a two bus parallel system there are two 32-bit lfsr signature logic blocks on the both the lvds and sync blocks. figure 30 shows where the lvds and sync phases are located. figure 30. block diagram showing lvds and sync phase 1 and phase 2 bist operation the internal signature generator processes the input data to create the bist signatures. an external program which implements the same algorithm may be used to ge nerate the expected signature for comparison. a matlab routine can be provided upon request to perform this function. clock the test vector in as described below and compare the signature register values to the ex pected value to verify correct operation and input data capture. with all clocks running: 1. apply the idle vector to the data inputs (0x0000 if unsigned, 0x2000 if two's complement) for 1024 clocks, 2. set lvds_en (reg17, bit 2) and sync_en (reg17, bit 1) high, 3. set clear (reg17, bit 0) high, 4. set clear low to clear the bist signature register, 5. clock the bist vector into the lvds data inputs, 6. after the bist vector is complete, return the inputs to the idle vector value, 7. set lvds_en (reg17, bit 2) and sync_en (reg17, bit 1) low, 8. set the desired sel<1:0> bits and read back the four bist signature registers (reg18, 19, 20 and 21). when the dac is in 1x mode, the signature at sync bist, phase 1 should equal the signature at lvds bist, phase 1. the same is true for phase 2. bist does not support 2x mode. lvds rx figure 24 db<13:0> dataclk_in lvds bist ph1 lvds bist ph2 sync bist ph1 sync bist ph2 sync logic dac spi port d1 d2 fifo 2x
ad9736/ad9735/ad9734 preliminary technical data rev. prj | page 28 of 42 ad9736 analog control register the ad9736 includes some registers for optimizing its analog performance. these registers include temperature trim for the bandgap, noise reduction in the output current mirror and output current mirror headroom adjustments. bandgap temperature characteristic trim bits using trmbg<2:0> (reg14, bits 2:0) the temperature characteristic of the internal bandgap can be trimmed to minimize the drift over temperature as shown in figure 31. figure 31. bandgap temperature characteristic for various trmbg values it is important to note that the temperature changes are sensitive to process variations and the above plot may not be representative of all fabrication lots. optimum adjustment requires measurement of the device operation at two temperatures and development of a trim algorithm to program the correct trmbg<2:0> values in external non-volatile memory. mirror roll off frequency control with msel<1:0> (reg14, bits 7:6) the user can adjust the noise contribution of the internal current mirror to optimize the 1/f noise. figure 32 shows msel vs. the 1/f noise with 20ma full- scale current into a 50ohm resistor. figure 32. 1/f noise with respect to msel bits headroom bits hdrm<7:0> (reg15, bits 7:0) is for internal evaluation and it is not recommended to change them from their default reset values.
preliminary technical data ad9736/ad9735/ad9734 rev. prj | page 29 of 42 voltage reference the ad9736 output current is set by a combination of digital control bits and the i120 reference current as shown in figure 33. figure 33. voltage reference circuit the reference current is obtained by forcing the bandgap voltage across an external 10kohm resistor from i120 (pin b14) to ground. the 1.2v nominal bandgap voltage (vref) will generate a 120ua reference current in the 10k resistor. this current is adjusted digitally by fsc<9:0> (reg02, reg03) to set the output full scale current i fs : ? ? ? ? ? ? ? ? ? ? ? ? ? ? > < + = 0 : 9 1024 192 2 7 r vref fsc i fs the full scale output current range is 10ma to 30ma for register values from 0x000 to 0x3ff. the default value of 0x200 generates 20ma full scale. the typical range is shown in figure 34 . 0 5 10 15 20 25 30 35 0 200 400 600 800 1000 dac gain code i fs (ma) figure 34. i fs vs. dac gain code vref (pin c14) must be bypassed to ground with a 1nf capacitor. the bandgap voltage is present on this pin and may be buffered for use in external circuitry. the typical output impedance is near 5kohms. if desired, an external reference may be used to overdrive the internal reference by connecting it to the vref pin. iptat (pin d14) is used for factory testing. it may be left floating (preferred) or tied to analog ground. it will output a current which is proportional to absolute temperature. the nominal output is approximately 10ua at 25c. the slope is approximately 20na per degree c. current scaling dac vbg 1.2v fsc<9:0> ifull-scale ad9736 i120 1nf vref i120 10k?
ad9736/ad9735/ad9734 preliminary technical data rev. prj | page 30 of 42 applications information fpga/asic dac driver requirements to achieve data synchronization using the high speed capability of the ad9736, adi recommends the configuration in figure 35 for the fpga/asic driving the digital inputs. using the double data rate dataclk_out, this configuration will generate the lvds dataclk_in to drive the ad9736 at the ddr rate. the circuit also synchronizes the dataclk_in and the digital input data (db<13:0>) as required by the ad9736. the synchronization engine in the ad9736 then uses dataclk_in to generate the internal clock sampling signal to capture the incoming data via the manual, surveillance or auto mode. to operate in 2x mode, the circuit in figure 35 must be modified to include a divide-by-two block in the dataclk_out path. without this additional divider the data and dataclk_in will be running 2x too fast. dataclk_out is always dacclk/2. figure 35. recommended fpga/asic configuration for driving ad9736 digital inputs, 1x mode figure 36. fpga/asic timing for driving ad9736 digital inputs, 1x mode timing error budget the following components make up the timing error budget for the ad9736: 1. ad9736 dataclk_out jitter 2. ad9736 dataclk_in jitter 3. db13:0 jitter 4. db13:0 skew from data source 5. db13:0 receiver skew margin (board + ad9736 internal delays) 6. db13:0 to dataclk_in skew from data source a c e b d a c b d a b c dataclk_out+ data1 data2 d1 d2 db dataclk_in+
preliminary technical data ad9736/ad9735/ad9734 rev. prj | page 31 of 42 ad9736 evaluation board schematics 0 1 2 1 c l 0 1 2 1 c l e s a c a e s a c a e s a c a e s a c a e s a c a 1 b n e g o r d y h f 0 t e e r t s n r u b o w 4 0 8 g n i r u t c a f u n a m n o t g n i m l i w e l a c s t o n o d e l a c s v e r r e b m u n g n i w a r d o n m c s f e z i s e n o n d e v o r p p a e t a d s n o i s i v e r n o i t p i r c s e d v e r 1 d c b a 1 2 3 4 a b c d 2 3 4 7 8 8 1 0 a m , n o t g n i m l i w : y b d e v o r p p a : y b n w a r d t e e h s m r j 8 2 . 8 0 3 0 . b v e r a g b c a d a g i g m o r f a t a d e c r u o s a 0 1 2 1 c l 0 1 2 1 c l 0 1 2 1 c l 0 1 2 1 c l a s s v a s s v s s v s s v t u d r e d n u s r e t l i f t u p n i r e w o p 9 1 . 5 0 4 0 = e t a d e l i f a n a 8 1 a n a 3 3 g i d 8 1 s s v g i d 3 3 e t i r r e f 7 l a 8 1 d d v b 8 1 d d v 3 3 d d v 3 3 a d d v a s s v e t i r r e f 1 l e t i r r e f 4 l e t i r r e f 3 l a s s v 1 1 p t k l b c d d v c 5 a s s v 1 p j s s v 3 1 p t k l b k l b 4 1 p t 3 p t k l b 4 p t d e r 5 p t k l b d e r 6 p t 1 p t d e r 2 2 c f u 0 1 v 3 . 6 8 1 c f u 0 1 v 3 . 6 4 1 c f u 0 1 v 3 . 6 0 1 c f u 0 1 v 3 . 6 1 c f u 0 1 v 3 . 6 e t i r r e f 6 l e t i r r e f 5 l 1 1 b t 4 2 b t 3 2 b t 2 2 b t 1 2 b t 4 1 b t 3 1 b t 2 1 b t d e r 7 p t d e r 9 p t s s v s s v figure 37. power supply inputs for ad9736 evaluation board, rev c
ad9736/ad9735/ad9734 preliminary technical data rev. prj | page 32 of 42 b a 3 0 6 0 c c 3 0 6 0 c c 3 0 6 0 c c e s a c a 3 0 6 0 c c 3 0 6 0 c c e s a c a 3 0 6 0 c c 3 0 6 0 c c e s a c a e s a c a 3 0 6 0 c c e s a c a 3 0 6 0 c c 3 0 6 0 c c rc1206 3 0 6 0 c c 3 0 6 0 c c 3 0 6 0 c c 3 0 6 0 c c 3 0 6 0 c c 3 0 6 0 c c n e g o r d y h 2 3 3 a s s v 1 3 3 a s s v 4 3 3 a s s v 5 3 3 a d d v 6 3 3 a d d v 7 1 3 3 a s s v 6 1 3 3 a s s v 1 2 3 3 a s s v 0 2 3 3 a s s v 2 n i p k l c n k l c 2 1 3 3 a s s v 1 1 3 3 a s s v 0 1 3 3 a s s v 9 3 3 a s s v 8 3 3 a s s v 7 3 3 a s s v 1 c s s v 1 1 c d d v 8 c d d v 7 c d d v 5 c d d v 4 c d d v 3 c d d v b s c _ x 2 o i d s _ o f i f 9 c s s v 8 c s s v 5 c s s v 4 c s s v 3 c s s v 2 c s s v k l c s _ 0 c s f o d s _ 1 c s f 1 d l e i h s 2 d l e i h s 5 d l e i h s 6 d l e i h s 1 1 c s s v 0 1 c s s v 7 3 3 a d d v 8 3 3 a d d v 0 2 1 i e r a p s t a t p i 4 3 3 a d d v 2 3 3 a d d v 4 2 3 3 a s s v 3 1 3 3 a s s v 3 p i 3 n i 2 c d d v 0 1 c d d v 7 c s s v 4 d l e i h s t e s e r _ d p 3 3 3 a d d v 1 3 3 a d d v 3 2 3 3 a s s v 2 2 3 3 a s s v 9 1 3 3 a s s v 8 1 3 3 a s s v 5 1 3 3 a s s v 4 p i 4 n i 3 3 3 a s s v 5 3 3 a s s v 1 c d d v 9 c d d v 6 c s s v 3 d l e i h s q r i _ d e n g i s 1 p i 2 p i f e r v 6 3 3 a s s v 6 c d d v 4 1 3 3 a s s v 1 n i p o t n e g o r d y h 6 d d v 5 d d v 8 d d v n 2 1 s d v l p 2 1 s d v l 0 2 s s v 9 d d v 6 1 s s v 7 1 s s v 2 d d v 8 s s v 4 s s v 3 s s v p 2 s d v l n 2 s d v l p 0 s d v l n 0 s d v l e d o m _ i p s 2 2 s s v 1 k c n 1 2 s s v n 7 s d v l p 7 s d v l p 5 s d v l n 5 s d v l p 4 s d v l n 4 s d v l n 6 s d v l p 6 s d v l n n i k l c s d v l p n i k l c s d v l 6 3 3 d d v 5 3 3 d d v 4 3 3 d d v 3 3 3 d d v p 1 1 s d v l p 0 1 s d v l n 0 1 s d v l p 9 s d v l p 3 1 s d v l 1 1 s s v 3 1 s s v 2 1 d d v 3 d d v 2 s s v 0 1 s s v p 1 s d v l p t u o k l c s d v l 7 3 3 d d v p 8 s d v l n 3 1 s d v l 2 1 s s v 4 1 s s v 5 1 s s v 8 1 s s v 9 1 s s v 0 1 d d v 1 1 d d v 4 d d v 1 s s v 9 s s v n 1 s d v l n t u o k l c s d v l 8 3 3 d d v n 8 s d v l 6 1 d d v 1 d d v n 9 s d v l 7 d d v 5 s s v 7 s s v 6 s s v 4 1 d d v 5 1 d d v 3 1 d d v 1 3 3 d d v 2 3 3 d d v n 3 s d v l p 3 s d v l n 1 1 s d v l m o t t o b 2 v e r 1 d c b a 1 2 3 4 a b c d 2 3 4 f o b a 3 0 6 0 c r q r i a _ t e s e r t e s e r jp3 3 3 a d d v q r i 3 3 d d v 3 3 d d v k 0 1 6 1 r t h w 2 p t 3 3 d d v 3 1 2 8 p j jp4 a s s v 5 n e g o r d y h c 2 j 1 j 4 j 3 1 l 4 1 l 1 1 k 1 1 j 1 1 l 0 1 l 2 h 4 m 4 l 3 l 2 p 2 n 1 m 2 m 1 l 2 l 1 k 2 k 1 1 n 1 1 p 5 p 5 n 4 p 4 n 0 1 n 0 1 p 9 n 9 p 8 n 8 p 7 p 7 n 4 1 m 4 1 p 4 1 n 3 1 p 4 1 k 2 1 m 0 1 m 4 1 j 3 h 4 k 6 m 1 p 6 p 8 m 2 1 p 3 1 k 1 1 m 9 m 2 1 l 9 l 2 1 k 2 1 j 3 1 j 4 h 3 k 5 m 1 n 6 n 8 l 2 1 n 4 1 h 1 h 3 1 n 3 j 5 l 3 m 6 l 2 1 h 3 1 h 1 1 h 7 l 7 m 3 n 3 p 3 1 m 1 u 5 a 4 a 4 b 2 1 c 3 1 c 0 1 b 9 b 1 1 c 0 1 c 7 b 1 f 1 e 6 d 5 d 4 d 6 c 5 c 4 c 1 d 3 d 2 c 1 c 2 b 1 b 3 a 3 1 f 4 1 f 2 g 1 g 2 f 4 e 3 e 2 e 3 1 g 4 1 g 1 1 e 2 1 e 1 1 g 2 1 g 4 g 3 g 2 1 d 3 1 d 4 1 b 4 1 a 4 1 d 3 1 b 3 1 a 1 1 d 9 a 8 c 7 c 2 a 2 d 4 f 2 1 f 4 1 e 2 1 b 2 1 a 0 1 d 9 d 9 c 1 1 b 1 1 a 8 d 7 d 6 a 5 b 1 a 3 c 3 f 1 1 f 3 1 e 8 a 8 b 4 1 c 6 b 3 b 0 1 a 7 a 1 u t a t p i 2 1 p t t h w f n 1 9 c % 1 . k 0 0 . 0 1 1 r s s v 7 c p n d a 8 1 d d v p n d 8 c 6 c p n d p n d 5 c 3 c f u 1 . 0 t h w 0 1 p t 0 2 1 i t h w 8 p t f e r v n i p k l c d s s v 5 r k 0 1 3 1 c f n 1 4 c f n 1 a s s v 1 1 c f u 7 . 4 v 3 . 6 2 1 c f u 1 . 0 2 c f u 7 . 4 v 3 . 6 1 3 2 4 1 w s 5 ; s s v 5 1 c f u 7 . 4 v 3 . 6 6 1 c f u 1 . 0 7 1 c f n 1 3 2 c f u 7 . 4 v 3 . 6 4 2 c f u 1 . 0 5 2 c f n 1 9 1 c f u 7 . 4 v 3 . 6 0 2 c f u 1 . 0 1 2 c f n 1 n 3 1 b d p 3 1 b d n 2 1 b d p 2 1 b d n 1 1 b d p 1 1 b d n 0 1 b d p 0 1 b d n 9 b d p 9 b d n 8 b d p 8 b d t u o n k l c d t u o p k l c d n i n k l c d p 7 b d n 7 b d p 6 b d n 6 b d p 5 b d n 5 b d p 4 b d n 4 b d p 3 b d n 3 b d p 2 b d n 2 b d p 1 b d n 1 b d p 0 b d n 0 b d n i p i a s s v o d s p s k l c p s i d s p s b s c p s n k l c p k l c a s s v 4 3 c p n d c d d v a s s v b 8 1 d d v s s v 3 3 d d v t h w 6 1 p t e r a p s 2 3 1 5 1 p j s s v s s v figure 38. circuitry local to ad9736, evaluation board, rev c
preliminary technical data ad9736/ad9735/ad9734 rev. prj | page 33 of 42 fcn-268 f024-g/0 d jack jack v e r 1 d c b a 1 2 3 4 a b c d 2 3 4 f o 5 3 n e g o r d y h c n 3 1 b d n 2 1 b d p 3 1 b d p 2 1 b d p t u o t s e t n t u o t s e t 5 1 p t t h w s s v p 1 1 b d k l c t x e p 0 1 b d p 8 b d p 7 b d n 7 b d n 6 b d n 0 b d n 1 b d n 2 b d n 3 b d n 4 b d n 5 b d p 0 b d p 1 b d p 2 b d p 3 b d p 4 b d p 5 b d g2 1 s s2 g3 g4 s3 s4 g5 g6 s5 s6 g7 g8 s7 s8 g9 g10 s9 s10 g11 g12 s11 s12 g13 g14 s13 s14 g15 g16 s15 s16 g17 g18 s17 s18 g19 g20 s19 s20 g21 g22 s21 s22 g23 g24 s23 s24 g25 g26 s25 s26 g27 g28 s27 s28 g29 g30 s29 s30 g31 g32 s31 s32 g33 g34 s33 s34 g35 g36 s35 s36 g37 g38 s37 s38 g39 g40 s39 s40 g41 g42 s41 s42 g43 g44 s43 s44 g45 g46 s45 s46 g47 g48 s47 s48 g49 g50 g1 3 j n i n k l c d t u o n k l c d n 8 b d n 9 b d n 0 1 b d n 1 1 b d p 6 b d n i p k l c d t u o p k l c d p 9 b d figure 39. high speed digital i/o connector, ad9736 evaluation board, rev c
ad9736/ad9735/ad9734 preliminary technical data rev. prj | page 34 of 42 3 1 - 1 - 1 c t e 2 = c n p s cc0603 3 0 6 0 c c 3 0 6 0 c r 3 0 6 0 c r 3 1 - 1 - 1 c t e 2 = c n s p 3 0 6 0 c r rc0603 rc0603 3 0 6 0 c c 3 0 6 0 c c rc0603 x x 2 1 - 1 l t d a s p rc0603 rc0603 rc0603 3 0 6 0 c c 3 0 6 0 c r 3 0 6 0 c r 3 0 6 0 c r v e r 1 d c b a 1 2 3 4 a b c d 2 3 4 f o 3 0 6 0 c c cc0603 p 1 - t 1 - 2 t d a s p p 1 - t 1 - 2 t d a s p 3 1 - 1 - 1 c t e 2 = c n p s a s s v 3 5 1 4 b 4 t a s s v 1 2 3 4 5 6 1 t 6 5 3 4 2 1 2 t p k l c n k l c 5 3 c f u 1 . 0 8 2 c f u 1 . 0 a s s v 5 4 n e g o r d y h c 2 6 1 r p n d 1 6 1 r p n d 7 1 r p n d 7 2 c p n d n i p i 8 r p n d 6 r p n d 7 r 9 . 9 4 1 4 3 6 a 3 t 3 r k 1 p u 0 0 2 a m s 1 j 5 , 4 , 3 ; a s s v p u 0 0 2 a m s 5 , 4 , 3 ; a s s v 2 j 9 2 c f n 1 6 2 c p n d 4 r 0 0 3 8 1 r p n d 9 1 r p n d a s s v a s s v 3 1 5 4 b 3 t 5 2 0 2 r 5 2 1 2 r f n 1 8 3 c c d d v a s s v f u 1 . 0 6 3 c 4 5 1 3 3 t figure 40. clock input and analog output, ad9736 evaluation board, rev c note: t1, t3 & t3b are installed, r6 & r8 = 50 ohms, r17 & r19 = 20 ohms, r161 & r162 = 0 ohms, r7 = open jumper added from t1 pin 3 to t1 pin 2 jumper added
preliminary technical data ad9736/ad9735/ad9734 rev. prj | page 35 of 42 b a b a 2 4 1 c a 4 7 4 1 c a 4 7 4 1 c a 4 7 4 1 c a 4 7 4 1 c a 4 7 4 1 c a 4 7 4 1 c a 4 7 4 1 c a 4 7 4 1 c a 4 7 4 1 c a 4 7 5 0 8 0 c r 5 0 8 0 c r 5 0 8 0 c r rc0603 rc0603 0 1 2 1 c l 0 1 2 1 c l e s a c a 5 0 8 0 c c e s a c a 5 0 8 0 c c 4 1 c a 4 7 2 b a 4 1 c a 4 7 b a b a b a v e r 1 d c b a 1 2 3 4 a b c d 2 3 4 f o t r o p i p s 5 5 n e g o r d y h c a _ t e s e r 3 1 2 3 1 p j 5 p j b s c p s 2 3 1 4 1 p j k l c p s 6 p j i d s p s 2 3 1 9 p j 7 p j 0 1 1 1 4 1 ; 3 3 d d v 7 ; s s v 6 u o d s p s 3 1 2 0 1 p j 2 p j q r i 8 9 6 u 7 ; s s v 4 1 ; 3 3 d d v 3 3 c f u 1 . 2 3 c f u 7 . 4 v 3 . 6 1 3 c f u 1 . 0 3 c f u 7 . 4 v 3 . 6 e t i r r e f 9 l 6 1 2 4 5 3 1 p s s v s s v e t i r r e f 8 l k 0 1 4 1 r 3 1 r k 0 1 k 9 2 1 r k 9 1 1 r k 9 0 1 r 3 4 4 1 ; 3 3 d d v 7 ; s s v 5 u 1 2 5 u 7 ; s s v 4 1 ; 3 3 d d v 2 1 4 1 ; 3 3 d d v 7 ; s s v 6 u 3 3 d d v 2 1 3 1 6 u 7 ; s s v 4 1 ; 3 3 d d v 1 1 0 1 4 1 ; 3 3 d d v 7 ; s s v 5 u 3 1 2 1 5 u 7 ; s s v 4 1 ; 3 3 d d v 5 6 5 u 7 ; s s v 4 1 ; 3 3 d d v 6 5 6 u 7 ; s s v 4 1 ; 3 3 d d v 4 3 4 1 ; 3 3 d d v 7 ; s s v 6 u 9 8 4 1 ; 3 3 d d v 7 ; s s v 5 u s s v 3 3 d d v s s v 3 3 d d v s s v 3 3 d d v s s v 3 3 d d v s s v 3 3 d d v 2 3 1 1 1 p j s s v 3 3 d d v 3 1 2 2 1 p j figure 41. spi port interface, ad9736 evaluation board, rev c
ad9736/ad9735/ad9734 preliminary technical data rev. prj | page 36 of 42 ad9736 evaluation board pcb layout figure 42. pcb layout top placement, ad9736 evaluation board, rev c note: ad9736 is soldered directly to the pcb, the socket is not installed. silkscreen error: spi pin
preliminary technical data ad9736/ad9735/ad9734 rev. prj | page 37 of 42 figure 43. pcb layout layer 1, ad9736 evaluation board, rev c
ad9736/ad9735/ad9734 preliminary technical data rev. prj | page 38 of 42 figure 44. pcb layout layer 2, ad9736 evaluation board, rev c
preliminary technical data ad9736/ad9735/ad9734 rev. prj | page 39 of 42 figure 45. pcb layout layer 3, ad9736 evaluation board, rev c
ad9736/ad9735/ad9734 preliminary technical data rev. prj | page 40 of 42 figure 46. pcb layout layer 4, ad9736 evaluation board, rev c
preliminary technical data ad9736/ad9735/ad9734 rev. prj | page 41 of 42 figure 47. pcb layout bottom placemen t, ad9736 evaluation board, rev c
ad9736/ad9735/ad9734 preliminary technical data rev. prj | page 42 of 42 figure 48. pcb fabrication detail, ad9736 evaluation board, rev c note: special layer stack to control lvds trace impedance.

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